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Referring now to FIGS. 1 and 2, a functional block diagram of prior art time-domain-based turbo coder is shown. A turbo encoder 10 includes a first encoder 12 and a second encoder 14. The first encoder 12 may include a processor 16 and one or more memory buffers 18 and 20. The second encoder 14 may include a processor 22 and one or more memory buffers 24 and 26. The processor 16 includes one or more digital processing circuits for encoding input data received from the memory buffer 18. The processor 22 includes one or more digital processing circuits for encoding input data received from the memory buffer 24.
Referring now to FIG. 3, a functional block diagram of an example of a prior art interleaver is shown. A multi-block interleaver 30 includes a processor 32 and a memory buffer 34. The processor 32 may include one or more digital processing circuits for interleaving input data. The memory buffer 34 may include one or more memory cells for storing the input data.
Referring now to FIG. 4, a functional block diagram of an example of a prior art deinterleaver is shown. A deinterleaver 40 includes a processor 42 and one or more memory buffers 44. The processor 42 may include one or more digital processing circuits for deinterleaving the interleaved data. The memory buffer 44 may include one or more
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